1. Field of the Invention
The present invention relates to a semiconductor device. More particularly, it relates to a semiconductor device equipped with bonding pads on an active region thereof where active elements such as transistors are arranged.
2. Description of the Related Art
There has been a trend of downsizing of various devices in recent years and semiconductor devices to be incorporated therein are required to be also downsized. Particularly, compound semiconductor devices capable of operating for switching a high voltage and a large electric current if compared with silicon semiconductor devices are required to be downsized in response to a trend of development of high density switching power supply devices adapted to higher power supplies because power semiconductor devices are utilized there as switching elements. However, while an active region (of switching power supply devices) where active elements such as transistors and integrated circuits are arranged can be downsized to a certain extent, bonding pads for connecting active elements such as transistors and integrated circuits and packages and mounted substrates typically by wire bonding are arranged in a region surrounding the active region and a relatively large metal surface is required for wire bonding so that it is not easy for a semiconductor device to be downsized as a whole.
To date, two methods have been proposed to arrange bonding pads for a semiconductor device that needs to be downsized. One is a method of arranging some of the bonding pads at the backside of the substrate (see, for example, Patent Document 1: Jpn. Pat. Appln. Laid-Open Publication No. 2009-124002) and the other is a method of arranging some of the bonding pads above the active region thereof (see, for example, Patent Document 2: Jpn. Pat. Appln. Laid-Open Publication No. 2005-166959 and Patent Document 3: Jpn. Pat. Appln. Laid-Open Publication No. 2006-5202).
Firstly, the method of arranging some of the bonding pads at the backside of a substrate will be described below. A semiconductor device to be used with this method has a structure in which a compound semiconductor layer is formed on an electroconductive substrate. Then, a groove running through the compound semiconductor layer and getting to the electroconductive substrate is formed in order to reduce the number of bonding pads and downsize the chip. A source electrode to be connected to the source region of the compound semiconductor layer and also to the electroconductive substrate and an insulating layer for electrically insulating the source electrode from the compound semiconductor layer other than the source region are formed in the inside of the groove. A semiconductor device having such a structure can be downsized by forming a back surface electrode on the back surface of the electroconductive substrate because the back surface electrode can be utilized as a bonding pad for the source electrode.
Now, the method of arranging some of the bonding pads above the active region will be described below. A semiconductor device to be used with this method has a semiconductor substrate with an active region and a first insulating layer for isolating the active region formed thereon, a second insulating layer formed on the semiconductor substrate including the active region and the first insulating layer, a wiring layer formed on the second insulating layer, a third insulating layer formed on the second insulating layer and the wiring layer, an interconnection via for electrically connecting the active region and the wiring layer, one or more first vias for reinforcement formed on the first insulating layer or the second insulating layer on the semiconductor substrate, a passivation layer and bonding pads, the passivation layer and the bonding pads being formed on the active region. This semiconductor device can be downsized by reducing the area of the bonding pads as the bonding pads are arranged on the active region.
For known semiconductor devices having a structure in which some of the bonding pads thereof are arranged on the backside of the substrate, the insulating layer formed in the inside of the groove running through the compound semiconductor layer and getting to the electroconductive substrate needs to be partly etched to form a source electrode by dry etching (RIE) a part of the insulating layer. At that time, dry etching of the insulating layer is an indispensable process, however, it is difficult to accurately conduct a process of dry etching the insulating layer and, if the dry etching process is not conducted accurately, some of the characteristics of the semiconductor device can degraded. More specifically, if the insulating layer is not sufficiently etched by dry etching, the insulating layer can partly remain between the source region of the compound semiconductor layer and the source electrode to give rise to a problem of raising the contact resistance of the source electrode. If, on the other hand, the insulating layer is excessively etched by dry etching, the surface of the compound semiconductor layer is damaged by dry etching to give rise to a problem of raising the channel resistance and generating electric current collapses.
For known semiconductor devices having a structure in which some of the bonding pads are arranged above the active region of the device, the semiconductor layer in the active region is affected by changes in the electric potentials of the bonding pads arranged above the active region to give rise to a problem that some of the characteristics of the semiconductor device can be degraded.